(a) Field
The present disclosure relates to an inverter type of a power amplifier, and more particularly, to an inverter type of a power amplifier that may generate a self-bias voltage of a direct current (DC) component.
(b) Description of the Related Art
A power amplifier, which is one of circuits which are generally used in a high frequency integrated circuit for a wireless communication system and a hybrid circuit, is used to amplify a signal that is applied thereto. There are many types of power amplifiers, and an inverter type power amplifier is one of those that are widely used.
FIG. 1 illustrates a schematic circuit diagram of a typical inverter type power amplifier.
As shown in FIG. 1, a typical inverter type power amplifier 100 includes a power source voltage port VDD and ground port GND applying each a power source voltage and a ground, an input port (RFin) to which an input signal is inputted, and an output port (RFout) from which an output signal is outputted.
Transistors of the typical inverter type power amplifier 100 may include a PMOS 110 and a NMOS 120. A drain of the PMOS 110 is connected to the output port (RFout), a gate of the PMOS 110 is connected to the input port (RFin), and a source of the PMOS 110 is connected to the power source voltage port VDD. A drain of the NMOS 120 is connected to the output port (RFout), a gate of the NMOS 120 is connected to the input port (RFin), and a source of the NMOS 120 is connected to the ground port GND.
In addition, a feedback resistor 130 is disposed between the output port and the input port to interconnect the output port and the input port. The feedback resistor has a relatively great resistance so that transmission of an AC signal is suppressed and only a DC voltage is supplied, thereby applying a bias voltage to the PMOS 110 and the NMOS 120. If the PMOS 110 and the NMOS 120 have the same performance, a outputted DC voltage of the output port is a voltage of VDD/2. That is, a DC voltage of the output port is determined depending on performance of the PMOS 110 and NMOS 120.
FIG. 2 illustrates a schematic circuit diagram of an inverter type power amplifier according to the conventional art.
As shown in FIG. 2, a DC blocking block 231 interconnecting a gate of a PMOS 210 and the input port and a DC blocking block 232 interconnecting a gate of a NMOS 220 and the input port are further formed in the power amplifier shown in FIG. 1. Further, DC power sources 251 and 252 are respectively formed at the gate sides of the PMOS 210 and the NMOS 220 so that DC voltages are respectively supplied to the PMOS 210 and the NMOS 220, and AC blocking blocks 241 and 242 are respectively formed between the gate of the PMOS 210 and the DC power source 251 and between the gate of the NMOS 220 and the DC power source 252 so as to prevent an AC signal form being leaked to the DC power source.
It is preferable to suppress a through-current that the DC power source 251 substantially supplies about a threshold voltage of the PMOS 210 and the DC power source 252 substantially supplies about a threshold voltage of the NMOS 220. As such, when the voltages of the DC power sources 251 and 252 are adjusted, since a period in which the PMOS 210 and the NMOS 220 are simultaneously turned on can be adjusted, a through current can be adjusted. However, in this case, since an additional DC power source is added, a circuit and a system are complexified.
Background technology of the present disclosure is disclosed at Korean Patent Laid-Open Publication No. 2007-0068239 (Jun. 29, 2007).
The above information disclosed in this Background section is only to enhance the understanding of the background of the disclosure and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.